C2S: A Complete Guide to India's Chips to Startup Programme

India's ambition to become a global semiconductor hub runs into a basic constraint: chip design demands a highly specialised skillset that general engineering degrees simply do not produce at scale, and building a functioning startup ecosystem around that skillset takes years of deliberate capacity building, not just factories and fabs.

C2S, the Chips to Startup Programme, is the Ministry of Electronics and Information Technology's direct response. Launched in 2022 as an umbrella capacity building initiative with a total outlay of Rs. 250 crore over five years, C2S was built to democratise access to advanced chip design capability, transforming students, researchers, and entrepreneurs, irrespective of institution or location, into contributors to India's semiconductor design ecosystem. Today, it anchors the workforce side of India's broader Semicon India Programme.

The Opportunity: What C2S Actually Offers

• A serious talent development mandate: the programme is aimed at developing 85,000 industry ready B.Tech, M.Tech, and PhD professionals with expertise in VLSI, Very Large Scale Integration, and embedded system design within five years, alongside a target of developing 175 ASICs, Application Specific Integrated Circuits, and working prototypes.
• Direct project level funding: funding assistance of up to Rs. 15 lakh per approved project is available for eligible institutions and startups, covering chip design work, applied research, and prototype development.
• Institutional backbone with real tools access: the programme is implemented in collaboration with C DAC, the Centre for Development of Advanced Computing, and the ChipIN Centre, giving participating institutions and startups access to industry grade EDA, Electronic Design Automation, tools, access that would otherwise be prohibitively expensive for most participants.
• A genuine research to startup pipeline: C2S is explicitly framed as a mechanism for incentivising academic chip design projects to evolve into hardware startups, backed by seed funding and mentorship, not just a training programme that ends at graduation.
• Nationwide institutional reach: the programme covers around 300 organisations, roughly 250 of them academic institutions and around 65 startup firms, with over 1 lakh individuals enrolled in chip design training and approximately 67,000 trained so far. The ChipIN Centre has run 6 shared wafer runs and more than 265 training sessions with industry partners.
• Regional nodal hubs: clusters such as the Delhi NCR hub mentor smaller, tier two engineering colleges in chip design methodologies, spreading capability beyond India's traditional technology hotspots.

An important 2026 update: C2S now operates alongside a much larger commercial scheme, Semicon 2.0, notified by MeitY on August 31, 2026 following the Union Cabinet's approval of the India Semiconductor Mission 2.0 outlay. Semicon 2.0 carries a Rs. 1.27 lakh crore outlay across six pillars and 10 categories, and eligible startups and MSMEs under it can access milestone linked seed funding of 50 percent of project cost or Rs. 15 crore, whichever is lower, plus equity co investment for VC backed companies and royalty financing for larger firms. For newly launched semiconductor IP, chips, or SoCs, eligible applicants can also receive a 9 percent reimbursement on net sales for five years, capped at Rs. 30 crore per application and Rs. 120 crore per company including group companies. If your chip design venture has outgrown the academic and prototype scale that C2S is built for, Semicon 2.0 is the natural next step in the same ecosystem.

Who is eligible

• Academic institutions, R&D organisations, startups, and MSMEs working on VLSI design, embedded systems, or chip architecture development.
• Students and researchers building semiconductor solutions, regardless of which institution they belong to or where they are located.
• For the newer, larger commercial track, Semicon 2.0: companies incorporated and headquartered in India, owned and controlled by Indian citizens or Overseas Citizens of India, with a significant operational and manpower presence in the country, able to participate independently or in consortiums with global companies, R&D organisations, and academic institutions.

How the process works

1. Determine whether you are applying at the academic or prototype stage, C2S, or the commercial chip design stage, Semicon 2.0. Funding scale and eligibility criteria differ sharply between the two.
2. For C2S, apply through your academic institution or in partnership with C DAC and the ChipIN Centre when MeitY opens its periodic call for applications. Recent calls have invited proposals from academia, R&D organisations, startups, and MSMEs together.
3. For Semicon 2.0, prepare project documentation establishing incorporation status, ownership structure, and clear project milestones, since funding is milestone linked rather than disbursed upfront.
4. Once approved, gain access to EDA tool support, technical mentorship through C DAC and regional nodal hubs, and staged funding tied to design and prototype milestones.

The Institutions Powering C2S

C2S runs through MeitY's Innovation and IPR division in close collaboration with C DAC and the ChipIN Centre, which together provide end to end enablement for chip design education and innovation. By integrating R&D institutions and industry partners into a single institutional framework, C2S supports indigenous chip design while advancing India's broader objective of a self reliant and globally competitive semiconductor design ecosystem, with MeitY providing overall policy direction, funding, and programme oversight.

Frequently Asked Questions

Is C2S meant for students, startups, or both?

Both. C2S is built as a pipeline. It trains students and researchers within academic institutions in VLSI and embedded system design, and it explicitly supports the transition of promising academic chip design projects into funded hardware startups.

How much project funding can I get through C2S?

Up to Rs. 15 lakh per approved project for eligible institutions and startups under the base C2S Programme. For larger scale commercial chip design, the newer Semicon 2.0 scheme offers substantially more, up to Rs. 15 crore in milestone linked seed funding.

What is the difference between C2S and Semicon 2.0?

C2S is the academic capacity building and early prototype programme, with project funding capped around Rs. 15 lakh. Semicon 2.0, notified in 2026, is a much larger commercial scheme, a Rs. 1.27 lakh crore outlay, aimed at startups and companies ready to design and launch chips commercially, offering seed funding up to Rs. 15 crore along with equity co investment and royalty financing options.

Do I need to be part of an academic institution to access C2S?

Not necessarily. The programme explicitly aims to empower students, researchers, and entrepreneurs irrespective of institution or location, though much of its infrastructure and tool access is currently channelled through the roughly 250 academic institutions already onboarded.

What tools or resources does C2S actually provide beyond funding?

Access to industry grade EDA, Electronic Design Automation, tools through partnerships with C DAC and the ChipIN Centre, tools that would otherwise be a major cost barrier for students and early stage startups working on chip design.

The Bottom Line

C2S represents India's foundational bet on solving the semiconductor talent and startup pipeline problem at the root, by making chip design education and tooling accessible far beyond the country's traditional engineering hubs, and by deliberately engineering a path from academic project to funded startup. For students, researchers, and early founders in VLSI or embedded systems design, C2S offers a genuinely rare combination of training, tools, and seed capital, and for those ready to scale into commercial chip design, the newly notified Semicon 2.0 scheme picks up exactly where C2S leaves off. The practical next step is identifying whether your current stage fits C2S's academic or prototype scope or Semicon 2.0's commercial scale, then watching for MeitY's next call for applications.